Great progress has been made in ULSI technology and it has been a trend to increase the packaging density of devices. With this reduction of device size, many challenges arise in the manufacture of the ICs. Further, a various of specific requirements have been demanded to meet the such requirement. The large integration of semiconductor ICs has been accomplished by a reduction in individual device size. The formation of the ICs includes the fabrication of the wafer, the manufacture of the circuits and the package of the circuits. A so-called metallization involves the establishment of the connection between conductive structures. The purpose of the metallization includes constructing the connection between each terminal of the devices and connecting each device to perform a desired function. The typical material used for the metallization includes AlSiCu alloy and tungsten. The former exhibits superior conductive characteristic and the later is used for higher temperature process. The other material for semiconductor also includes tungsten silicide, titanium silicide and titanium nitride, etc.
Conductive structures between semiconductor devices are becoming more critical as the integrated circuits approaches to ever smaller submicron spectrums. A conductive path is formed by the interconnections between the devices, and effectively provides electrical connections between them. Interconnections between devices are typically constructed after the devices are formed on a semiconductor wafer. The isolated devices are interconnected through specific conducting paths to construct some desired function in an electrical circuit. At present, different interconnection technologies have been proposed and applied to the fabrication of integrated circuits. Furthermore, conductive metal plug technique is primly used in multi-level interconnection in VLSI and ULSI designs. In prior art, a metal layer is formed over a thick oxide layer, followed by etching the metal layer to a desired metal pattern by conventional lithography and etching technologies. A liner layer typical formed on the surface of the metal pattern to improve the adhension for subsequent layer. In general, the liner layer is composed of oxide. A spin on glass is then coated on the liner layer as an inter metal dielectric (IMD) layer. After that a further silicon oxide layer is deposited on the surface of the spin on glass, then a global planarization is performed to achieve better topography by chemical mechanical polishing (CMP). Subsequently, a via hole is opened through the IMD to the underlying metal pattern layer. A tungsten plug is successively formed in the via hole to complete the formation of the metalization.
One of the problems associated with the formation of metal connection is the parasitic capacitor. The design rule shrinkage of ULSI has led to increase interconnection delay caused by the parasitic capacitance of wiring. To reduce the RC time delay, one of the ways is to reduce the dielectric constant of inter metal dielectric layer. The capability of thermal dispersal is a further major consideration for the interconnection. At present, the organic material is widely used for IMD due to the organic material has lower dielectric constant, therefore, it can reduce the RC time delay, effectively. However, the thermal conductivity of the organic material is poor, this leads to the thermal spreading efficient of the metal line is also bad. Thus, the reliability of the devices is degraded.